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Peraso Announces Knowledge Resources Has Chosen BE-3 Memory IC for FPGA Acceleration

Posted on June 23, 2022

San Jose, CA – June 23, 2022 – Peraso Inc. (NASDAQ:PRSO) (Peraso®), a leader in mmWave technology, today announced that Knowledge Resources GmbH, a sophisticated Electronics Design Services company located in Basel, Switzerland, is now using Peraso’s Bandwidth Engine 3 (BE-3) memory solution for its latest FPGA acceleration card. Knowledge Resources is previewing its KRM-20MSX module at Embedded World 2022, Hall 3A, Booth #335, June 21-23, Nurenberg, Germany.

“Knowledge Resources GmbH has been looking at an opportunity to deploy the BE3-RMW for some time,” stated Mike Stengle, CEO of Knowledge Resources. “By designing our new KRM-20 Module with the BE3-RMW, we have created an easy to deploy companion System on Module (SoM) for our high- end FPGA module families.”

Knowledge Resources chose Peraso’s BE3-RMW for its multi-level, high-performance SRAM memory with embedded In-Memory BURST functions for speed and ease-of-use. The solution combines a high- speed, serial protocol I/O interface with 1.1Gb of high access rate memory in a single package to further accelerate the high-performance Versal Premium VP1202 FPGA from Xilinx to enable a host of applications requiring high performance.

“Peraso is delighted that Knowledge Resources has chosen our proven memory technology,” stated Ron Glibbery, CEO of Peraso. “The BE-3 Accelerator Engine is designed to interface the memory to the Xilinx FPGA using 16 SerDes lanes to transmit data at up to 25Gbps, full duplex throughput, enabling up to 5 billion memory transaction per second. This is yet another example of the many customers who have designed in our high access rate memory ICs to accelerate their FPGA designs and offer more flexible and higher performance solutions.”

Key features of the BE-3 RMW include:page1image43797504

• 1.152 Gb memory with SerDes I/O

  • Accessible through as few as 4 Lanes and as many as 16

• Deterministic Latency
• Embedded In-Memory Functions

  • Burst 2, 4 or 8 Simultaneous Read/Writes
  • On chip ALU for RMW (Read/Modify/Write) functions enabling stats, counters and metering to be offloaded from host FPGA

• Two Separate Access Ports

  • Usable as a standard memory
  • Usable as a dual port between 2 FPGAs

For additional information on Knowledge Resources products: LINK

For additional information on Peraso’s Blazar Products: LINK

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